In response to demands for wideband wireless communication, IEEE802.11a as a new wireless LAN standard based on orthogonal frequency division multiplex (OFDM) provides about five times the data rate and at least 20 times the overall system capacity compared to the current IEEE802.11b wireless LAN system. OFDM stands for Orthogonal Frequency Division Multiplex, and LAN stands for Local Area Network.
The following non-patent document 1 describes that the IEEE802.11a wireless LAN system contains a physical layer (PHY) and a media access layer (MAC), and the physical layer is based on the orthogonal frequency division multiplex (OFDM). A modulation technique using multiple carriers reduces a multipath effect, and the OFDM distributes data into multiple carriers separated at accurate frequencies.
The non-patent document 1 describes that the 802.11a wireless LAN system contains a CMOS RF transceiver chip and a digital baseband chip. Dual conversion is adopted in the architecture of the receiver and transmitter of the RF transceiver without direct conversion being adopted therein. Reception baseband signals I and Q down-converted by the receiver are amplified by programmable gain amplifiers (PGA) through off-chip passive LC channel selection filters. The DC offsets of the outputs of the two programmable gain amplifiers are cancelled by two 6-bit D/A converters. DC offset cancellation, automatic gain control (AGC), frequency offset cancellation, timing offset cancellation, and received signal strength indicator (RSSI) are implemented by a digital algorithm of the baseband chip.
In the digital baseband chip, the reception baseband signals I and Q from the receiver of the RF transceiver are supplied to A/D converters, and the output digital signals of the A/D converters are supplied to autocorrelators through two FIR filters. The outputs of the A/D converters and the outputs of the autocorrelators are supplied to a signal detection AGC unit, and the DC offset and gain of the analog receiver are calibrated by the output of this unit. Automatic gain control (AGC) controls the gain of the receiver so as to maximize the reception signal without saturating inputs to the A/D converters to cope with adjacent channel interference, the peak value of reception OFDM symbols, and amplitude variation due to fading. A relatively short period of about 4 microseconds for automatic gain control (AGC) in 802.11a requires a fast loop from digital power measurement to analog gain adjustment. Signal detection, frequency offset estimation, and symbol timing depend entirely on autocorrelation of a period training symbol supplied to a preamble. Ten short preamble symbols each having a period of 0.8 microseconds are used to detect the presence of a frame (burst), calculate a carrier frequency supplied to a frequency rotator, and estimate symbol timing. Long preamble symbols which are two long training OFDM symbols each having a period of 4 microseconds are subjected to averaging, fast Fourier transform (FFT), and filtering. The output digital signals of the A/D converters are supplied to one FIR filter, DC offset elimination unit, frequency rotator, fast Fourier transformer (FFT), channel selection filter, and Viterbi decoder. Reception data to the media access layer (MAC) is generated from the output terminal of the Viterbi decoder. The fast Fourier transformer (FFT) shares hardware with an inverse fast Fourier transformer (IFFT) for the transmitter.
The following non-patent document 2 describes a wireless LAN transceiver that covers a first frequency band of 2.412 to 2.484 GHz complying with the IEEE802.11b/g standard and a second frequency band of 4.92 to 5.805 GHz complying with the IEEE802.11a standard. Due to low cost, low power consumption, design complexity, suitability for high integration density, and high-volume production capability, this transceiver adopts CMOS-process single-chip dual-band direct-conversion architecture.
On the other hand, the following patent document 1 describes a wireless LAN apparatus that includes a detection circuit for detecting the reception signal strength of a radio-frequency signal, a power supply control circuit for controlling the power supply of an intermediate-frequency signal processing unit of an analog part in response to the detection result of the signal strength, and an operation clock control circuit for controlling the supply of an operation clock to a digital demodulation unit, thereby reducing the power consumption during reception standby.    [Non-patent document 1] Teresa H. Meng et al, “Design and Implementation of an All-CMOS 802.11a Wireless LAN Chipset”, IEEE COMMUNICATION MAGAZINE, AUGUST 2003, PP. 160-168.    [Non-patent document 2] Pengfei Zhang et al, “A Single-Chip Dual-Band Direct-Conversion IEEE 802.11a/b/g WLAN Transceiver in 0.18-μm CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 9, SEPTEMBER 2005, PP. 1932-1939.    [Patent document 1] Japanese patent application laid-open No. 2006-020254.